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mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 1/23 version 0.90 toshiba mpeg-4 audiovisual lsi TC35273 tentative technical data sheet mpeg-4 audiovisual lsi features TC35273 is an mpeg-4 audiovisual codec lsi which supports 3gpp 3g-324m video telephony system. mpeg-4 video codec with qcif (176x144 pixel) at 15 frames/s, amr (adaptive multi rate) speech codec, and itu-t h.223 are executed concurrently at around 70mhz clock rate. three signal processing units, an mpeg-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. a 12-mbit embedded dram is integrated as a shared memory for the three signal processing units. the embedded dram helps to reduce power consumption without performance degradation. each signal processing unit consists of a 16-bit risc processor and dedicated hardware accelerators so as to bring programmability, high performance and low power consumption. firmware programs for the riscs are downloaded into the embedded dram before starting operation. various applications are performed by choosing an appropriate firmware. general host interface are adopted in order to support various host cpu. 2.5x to 6x of pll is integrated on the chip for easy system integration. ? toshiba continually is working to improve the quality and the reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. i t is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook. ? the products described in this document are subject to foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. p-fbga201-1515-0.80a5
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 2/23 version 0.90 ? the circuit contained herein is presented only as a guide for the applications, and it is not guaranteed.
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 3/23 version 0.90 1. functional specifications 1.1 mpeg-4 video codec iso mpeg-4 international standard simple profile @level 1 is supported. encoding and decoding with qcif (176 x 144 pixel) at 15 frames per second are executed. ycbcr 4:2:2 8bit digital camera input. a cmos camera or an ntsc decoder is connected. temporal filter and size conversion for pre-filter function. ycbcr 4:2:2 8bit digital display output. an ntsc encoder or an lcd controller is connected. size conversion and de-blocking filter for post-filter function. 1.1.1. speech codec / audio decoder amr speech codec at 8kbps with cs-acelp.* itu-t g.729 speech codec at 8kbps with cs-acelp.* itu-t g.723.1 speech codec at 5.3kbp with acelp, or 6.3kbps with mp-mlq. * stereo twin-vq audio decoder at 96kbps with up to 44.1-khz sampling frequency.* iso/iec 13818-7 aac lc audio decoder at 144kbps with up to 48-khz sampling frequency.* pcm stereo or monoral sound input/output. an external microphone and a speaker are connected via dac and adc, respectively. 1.1.2. multiplexer/demultiplexer multiplexing and demultiplexing with itu-t h.223 and h.223 annex a,b protocol at 32kbps 384kbps.* demultiplexing with itu-t h.222.0 / iso/iec13818-1 at 32kbps 1024kbps.* bitstream input/output via a network serial interface. * in order to run this lsi as an mepg-4 audiovisual lsi, specified firmware programs have to be obtained in advance
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 4/23 version 0.90 1.2. system configuration. fig. 1 illustrates a block diagram of this lsi. three signal processing core, peripheral interfaces, and 12-mbit dram are integrated in a single chip. bitstream input/output are performed via a network interface in the mux/demux core. a microphone and a speaker can be connected to a pcm interface in a speech/audio core via external dac and adc. toshiba cmos camera is connected to a camera interface via a camera dsp ?tc90a50f? or ?tc90a70f?. ntsc camera is also connected via an ntsc decoder. lcd or ntsc display is connected to an lcd interface via toshiba lcd controller or an ntsc encoder, respectively. host cpu is connected via a host interfaces. it downloads firmwares into the embedded dram and accesses to internal registers. fig. 1 block diagram 12mbit embedded dram arbiter + dram controller bitstream in/out cam. i/f lcd i/f pre- filter host i/f dma controller hw risc hw mpeg-4 video dma controller hw risc hw speech/audio dma controller hw risc hw mux./demux. d/a a /d lcdc camera dsp host cpu network bitstream interface
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 5/23 version 0.90 2. terminals 2.1 pin assignment tbd 2.2 pin allocation tbd 2.3 i/o pins fig. 2 pin map TC35273 mpeg-4 audiovisual lsi plldiv pllfn pllavd pllbp pllavs 3 /reset /hcs /hwr haddr /hrd hdat /hwait 7 16 /hack hint treout test0-3 nwclk /nwoen nwdo /nwien nwdi nwifs nwofs vgsadio vgsbdo vgsclk camclk camhref camvref camfsel campixel dispclk disphsync dispysync dispblk disppixel adimclk adomclk adlrclk adsclk adsdo adsdi adcmd pll pins host interface te s t p i n s network interface camera interface video general interface display interface audio pcm interface audio adc&dac control standby 8 8 tgclk tsmode tdbisten tdtmb tdtclk 5 4
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 6/23 version 0.90 table 1. system control signals signal name in/out bit width description /reset in 1 system reset input (low active). when the lsi is reset, the reset pin has to be low for more than 16 clock cycles. when power on, the lsi has to be reset after pll locked. it takes approximately 100us until the pll locked. standby in 1 system standby input (high active). when it is high, power is not supplied to the internal logic, sram, and dram. ?0?: normal operation. ?1?: standby. table 2. pll control signals signal name in/out bit width description pllfn in 1 reference clock input. it has to be 13.00mhz to 20mhz with +/- 10% duty. plldiv[2:0] in 3 system clock frequency select. system clock = pllfn * n. ?000?: n=2.5. ?001?: n=3.0. ?010? : n=3.5 ?011?: n=4.0. ?100?: n=4.5. ?101?: n=5:0. ?110?: n=5.5. ?111?: n=6.0. pllavd in 1 analog pll power (vdd). pllavs in 1 analog pll ground (vss). table 3. host interface signal name in/out bit width description /hcs in 1 chip enable input (low active). ?0? : chip select. ?1? : non operation. /hwr in 1 write strobe (low active). ?0? : write operation. ?1? : non operation. /hrd in 1 read strobe (low active). ?0? : read operation. ?1? : non operation. haddr[6:0] in 7 address signal. hdat[15:0] in/out 16 data signal. hwait out 1 bus wait signal (low active). ?0? : wait. ?1? : non wait. hint out 1 interrupt signal (high active). ?0? : non operation. ?1? : interrupt operation. table 4 video general serial interface signal name in/out bit width description vgsclk out 1 general i/f clock output. please open unless this interface is used. vgsadio in/out 1 input/output of serial data on port a. open unless this interface is used. vgsbdo out 1 output of serial data on port b. open unless this interface is used.
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 7/23 version 0.90
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 8/23 version 0.90 table 5 video camera interface signal name in/out bit width description camclk in 1 clock signal from camera. camhref in 1 href signal from camera. camvref in 1 vref signal from camera. camfsel in 1 field select signal from camera in an ntsc mode. campixel in 8 luminance and chrominance data from camera. table 6 video display interface signal name in/out bit width description dispclk in 1 clock signal from display. /disphsync in 1 hsync signal from display. /dispvsync in 1 vsync signal form display. /dispblk out 1 blanking signal to display. disppixel out 8 luminance (y) and chrominance (cb,cr) signal output. table 7 audio adc&dac interface signal name in/out bit width description adomclk out 1 master clock to external adc/dac chips. adimclk in 1 master clock from external adc/dac chips. adlrclk out 1 input/output channel clock to external adc/dac chips. adsclk out 1 audio serial data clock to external adc/dac chips. adsdi in 1 audio serial data input. adsdo out 1 audio serial data output. table 8 audio adc&dac control interface signal name in/out bit width description adcmd[4:0] out 5 command to external adc/dac chips. table 9 network bit stream interface signal name in/out bit width description nwclk in 1 network clock. /nwoen in 1 network bit serial output enable. /nwdo out 1 network bit serial output data. /nwien in 1 network bit serial input enable. nwdi in 1 network bit serial input data. nwifs in 1 word synchronization for input data in the frame mode. nwofs in 1 word synchronization for output data in the frame mode. nwint in 1 frame signal input in the frame mode.
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 9/23 version 0.90 table 10 test control signal signal name in/out bit width description tgclk in 1 test terminal. please connect to vss. tsmode in 1 test terminal. please connect to vss. tdbisten in 1 test terminal. please connect to vss. treout out 1 test terminal. please connect to open. tdtmb in 1 test terminal. please connect to vss. tdtclk in 1 test terminal. please connect to vss. test[2:0] in 3 test terminal. please connect to vss. table 11 power supply and gnd signal name in/out bit width description vss gnd vdds 3.3v vdd vdd2 2.5v vdd
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 10/23 version 0.90 3. interface specifications 3.1 host interface an external host cpu accesses to TC35273 via a host interface. the access timing of a read, a write, and an interrupt operation are explained below. the host interface has two access modes; a handshake access mode and a synchronized access mode. 3.1.1 handshake access mode in this mode, the host cpu has to finish an access operation after a waiting signal (/hwait) becomes high. fig.3 shows the timing diagram of a read operation. a read access starts by asserting both a chip select signal (/hcs) and a read signal (/rd) (timing (a)). at this timing, /hwait becomes low. w hen the read data are ready, /hwait becomes high (timing (b)). the host cpu gets the read data and finishes the read operation by negating both /hcs and /hrd (timing (c)). fig.4 shows the timing diagram of a write operation. a write access starts by asserting both /hcs and a write signal (/wr) (timing (a)). at this timing, /hwait becomes low. when TC35273 gets the write data, /hwait becomes high (timing (b)). after that, the host cpu finishes the write operation by negating both /hcs and /hwr (timing (c)). fig. 3 read operation in handshake mode haddr /hrd hdat /hwait /hcs t css t wtad t dtod t dtvd t dtrs t dtid t rdh t rr t adh t wtid t ads t csh (a) (b) (c)
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 11/23 version 0.90 fig. 4 write operation in handshake mode 3.1.2 synchronized access mode in this mode, a host cpu accomplishes an access to TC35273 in the specified period without a handshake. however, when the host cpu accesses to the embedded dram in TC35273, it has to check whether the next access is available or not by checking a status register before the access. fig.5 shows the timing diagram of a read operation. a read access starts by asserting both a chip select signal (/hcs) and a read signal (/rd) (timing (a)). after the specified cycles indicated as tacs, the host cpu gets the read data and finishes the read operation by negating both /hcs and /hrd (timing (b)). fig.6 shows the timing diagram of a write operation. a write access starts by asserting both /hcs and a write signal (/wr) (timing (a)). after the specified cycles, the host cpu finishes the write operation by negating both /hcs and /hwr (timing (b)). haddr /hwr hdat /hwait /hcs t css t wtad t dtws t dtid t rdh t rr t adh t wtid t ads t csh (a) (b) (c)
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 12/23 version 0.90 fig.5 read operation in synchronization mode fig.6 write operation in synchronization mode haddr /hrd hdat /hcs t css t wtad t dtod t dtvd t dtrs t dtid t rdh t rr t adh t ads t csh (a) (b) t acs haddr /hwr hdat /hcs t css t wtad t dtws t dtid t rr t adh t ads t csh (a) (c) t acs
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 13/23 version 0.90 3.1.3 interrupt an interrupt to the external host cpu is performed as follows. (a) hint active when an interrupt is requested by TC35273, hint becomes high (timing (a)). (b) clear hint the host cpu detects the interrupt request by hint. the cpu also detects the interrupt causes by reading an interrupt status register in the host interface of TC35273. when the cpu reads the register at the timing (b), the cpu detects the interrupt causes occurring during the timing (a) and (b). hint is cleared when the cpu reads the interrupt status register. (c) multiple interrupt even if another interrupt is requested during the timing (b) and (c), the assertion of hint is suspended to the timing (c). fig. 7 interrupt operation haddr /hrd hdat /hwait hint t rr d /hcs t acs (a) (b) (c)
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 14/23 version 0.90 table 12 host interface timing parameters description min max unit t css setup time of hcs. 0.0 ns t csh hold time of hcs. 0.0 ns t ads setup time of address. 0.0 ns t adh hold time of address. 0.0 ns t wtad delay time of /hwait for /hrd or /hwr. 15.0 ns t wtid access time in handshake access mode.* t sysclk *3 t sysclk *100 ns t acs access time in synchronized access mode. t sysclk *3 ns t acid delay time of hack 15.0 ns t dtod delay time of data. 15.0 ns t dtvd data hold time. t sysclk *2 t sysclk *99 ns t dtrs read data setup time. t sysclk *1 ns t dtws write data setup time. 0.0 ns t dtid data hold time. 15.0 ns t rdh hold time of /hrd. 0.0 ns t rr recovery time of /hrd or /hwr t sysclk *3 ns * t sysclk means the cycle time of tc35274 internal system clock. * access to internal dram requires tsysclk*100 (ns) in a worst case. as for the others accesses, it takes 3 cycles of the internal system clock.
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 15/23 version 0.90 3.2 video general serial interface this interface is reserved to control an external camera or an lcd. it is not supported now. 3.3 video camera interface a cmos camera or a ccd camera is connected via toshiba cmos camera dsp ?tc90a50f? or ?tc90a70f?, or an ordinary ntsc decoder lsi. fig.6, 7, 8 shows the timing diagrams of the camera signal input. when an ntsc decoder is used, TC35273 captures either an odd field or an even field by using camfsel. fig. 8 frame based camvref timing diagram fig. 9 field based (ntsc) camvref timing diagram camhref campixl camvref camvref camhref camfsel 1st field (even field) 2nd field (odd field) campixl
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 16/23 version 0.90 fig. 10 camera interface timing diagram table 13 camera interface timing parameter description min max unit t cycle clock cycle of camclk (up to 27mhz) 35 ns t setup setup time of camvref, camhref, campixel (t sysclk *1)+ 2 ns t hold hold time of camvref, camhref, campixl 2 ns camhref camvref campxl camclk cb0 cr0 y0 y1 t setup t hold t cycle y n-1
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 17/23 version 0.90 3.4 video display interface the video display interface outputs image data with ycbcr 4:2:2 8-bit digital format. an external lcd controller is required for the connection to an lcd or a monitor. fig. 11 timing diagram of display interface. fig. 12 detail timing diagram of display interface. /dispvsyn internal signal l2vbusy 1 cb0 /disphsyn 23 123 /dispblnk vblank=3 vsize=4 vblank=3 vsize=4 /disphsyn dispclk /dispblnk disppixel[7:0] hblank=4 hsize=2 hblank=4 y0 cr0 y1 cb0 y0 cr0y1 dspblk dsphsyn dspvsyn dsppxl dspclk cb0 cr0 y0 y1 t setup t hold t cycle y n-1 t delay
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 18/23 version 0.90 table 14 display interface timing parameter description min max unit t cycle cycle time of dispclk 100 ns t setup setup time of disphsyn and dispvsyn 2 ns t hold hold time disphsyn and dispvsyn 2 ns t delay delay time of dispblk and disppxl (t sysclk *3)+15 ns * when system clock is 40mhz, dspclk has to be less than 10mhz. 3.5 audio adc&dac interface asani-kasei ?ak4158? and ?ak4323? are connected for external adc and dac, respectively. fig. 13 audio adc&dac interface adsclk adsdi adlrclk adsdo t sckw t sdis t sdih t sdod adomclk t mckw t sckd t lckd h t lckd h
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 19/23 version 0.90 fig. 14 audio adc&dac interface (master clock output mode). table 15 audio adc&dac interface timing (master clock output mode). parameter description min max unit clock cycle period of adomclk. 80 ns t mckw duty ratio of adomclk. 50+/-10 % clock cycle period of adsclk. t mckw *8 ns t sckw delay time from adomclk to adkclk. t sysclk *2 ns t sdis setup time of adsdi. t sysclk *1 ns t sdih hold time of adsdi. t sysclk *4 ns t lckd delay time from adsclk to adlrlck. t sysclk *1 ns t sdod delay time from adsclk to adsdo. t sysclk *6 ns asclk alrck asdti asdto 15 16 clock cycles 14 13 12 11 1 0 15 14 13 12 11 1 0 0 0 15 15 14 14 13 13 rch data lch data
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 20/23 version 0.90 fig. 15 audio adc&dac interface (master clock input mode). table 16 audio adc&dac interface timing (master clock input mode). parameter description min max unit cycle time of adimclk. 80 ns t mckw duty ratio of adimclk. 50 10 % cycle time of adsclk. t mckw *8 ns t sckw delay time from adimclk to adsclk. t sysclk *3 ns t sdis setup time of adsdi. t sysclk *1 ns t sdih hold time of adsdi. t sysclk *4 ns t lckd delay time from adsclk to adlrlck. t sysclk *1 ns t sdod delay time from adsclk from adsdo. t sysclk *6 ns adsclk adsdi adlrclk adsdo t sckw t sdis t sdih t sdod adimclk t mckw t sckd t lckd h t lckd h
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 21/23 version 0.90 3.6 network bit stream interface the multiplexed audiovisual bitstream data are transferred to/from a baseband lsi via a network bit stream interface. this is full-dupulex interface and has two operation modes; a bit serial mode and a frame mode. (1) bit serial mode serial data are transferred when an enable signal indicates the data validity. in this mode, frame and synchronization informations are contained in the transferred data. TC35273 receives the transferred data via the nwdi pin at the negedge of the network clock ?nwclk? if the input enable signal ?nwien? shows the data validity. (when nwien is low, the data are valid.) TC35273 also sends the data via the nwdo pin at the posedge of nwclk if the output enable signal ?nwoen? is high. fig. 16 network bit stream timing diagram (bit serial mode). (2) frame mode the data are transferred in accordance with both a frame signal ?nwint? and a word synchronization signal. ?nwifs? and ?nwofs? are used for the word synchronization in the data receive and the data send, respectively. after nwifs or nwofs becomes high, 16-bit data are transferred. when the data transfer is finished in the frame, nwifs or nwofs does not becomes high. in this case, the output data are fixed to low, and the input data are ignored. nwclk /nwoen nwdo nwdi /nwien d1 d2 d3 d4 d5 d6 d7 d8 d9 d0 d1 d2 d3 d4 d5 d6 d7 d8 d0
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 22/23 version 0.90 fig. 17 network bit stream timing diagram (frame mode). nwclk nwifs nwdi d14 d2d1d0d15 d15 d14 d2 d1 d0 d15 nwofs nwdo d3 d2 d1 d0 d15 d15 d3 d2 d1 d0 nwint nwclk nwifs nwdi nwofs nwdo
mpeg-4 audiovisual codec lsi preliminary TC35273 toshiba confidential 2000-4-27 23/23 version 0.90 fig. 18 indicates the detail timing diagram of the network bitstream interface. fig. 18 detailed network bit stream interface. table 17 network bit stream timing. parameter description min max unit cycle time of nwclk. 1000 ns t sckw duty ratio of nwclk. 50+/-10 % t ens setup time of /nowen,/nwien, /nwint, nwofs, and nwifs t sysclk *3 ns t enh hold time of /nowen,/nwien, /nwint, nwofs, and nwifs t sysclk *1 2 ns t sdis setup time of nwdi t sysclk *3 ns t sdih hold time of nwdi t sysclk *1 2 ns t sdod delay time from nwclk to nwdo t sysclk *12 ns t sysclk is the cycle time of the internal clock in TC35273. 4. electric specifications 4.1 tbd. ?? nwclk /nwoen /nwien /nwint nwofs nwifs nwdi nwdo t sckw t enh t ens t sdih t sdis t sdod

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